| Item | Content | Total Test Case | Priority | Duration | Status |
|---|---|---|---|---|---|
| 1 | Power sequence | 3 | 1 | 2 | |
| 1.1 | Power On Sequence | 1 | 1 | 1 | |
| 1.2 | Power Off Sequence | 1 | 1 | 1 | |
| 1.3 | Power Leakage measurement | 1 | 1 | 1 | |
| 2 | Clock measurement | 1 | 3 | 3 | |
| 2.1 | Host Clock | 1 | 1 | 1 | |
| 2.2 | PCIe Clock | 1 | 1 | 1 | |
| 2.3 | Chipset Clock | 1 | 1 | 1 | |
| 3 | Function Enable/Disable | 3 | 1 | 3 | |
| 3.1 | Reset function | 1 | 1 | 1 | |
| 3.2 | Wake up function | 1 | 1 | 1 | |
| 3.3 | Alart function | 1 | 1 | 1 | |
| 4 | Memory Signal Margin | 2 | 1 | 2 | |
| 4.1 | Memory Write | 1 | 1 | 1 | |
| 4.2 | Memory Read | 1 | 1 | 1 | |
| 5 | PCIe Signal Margin | 1 | 1 | 4 | |
| 5.1 | PCISIG CEM Test | 1 | 1 | 1 | |
| 5.2 | Root Complex RX Margin | 1 | 1 | 1 | |
| 5.3 | LTSSM Stress test | 1 | 1 | 1 | |
| 5.4 | Function BER test | 1 | 1 | 1 | |
| 6 | Processor Link path SI Margin | 2 | 1 | 2 | |
| 6.1 | TX signal margin | 1 | 1 | 1 | |
| 6.2 | RX signal margin | 1 | 1 | 1 | |
| 7 | Chipset Memory SignalMargin | 2 | 1 | 2 | |
| 7.1 | Memory Write | 1 | 1 | 1 | |
| 7.2 | Memory Read | 1 | 1 | 1 | |
| 8 | I2C Signal Margin | 3 | 1 | 1 | |
| 8.1 | I2C far-end margin | 1 | 1 | 1 | |
| 8.2 | I2C near-end margin | 1 | 1 | 1 | |
| 8.3 | I2C Clock margin | 1 | 1 | 1 | |
| 9 | USB Signal | 2 | 1 | 2 | |
| 9.1 | USB Eye diagram | 1 | 1 | 1 | |
| 9.2 | USB power | 1 | 1 | 1 | |
| 10 | Ethernet signal | 2 | 1 | 1 | |
| 10.1 | IEEE measurement | 1 | 1 | 1 | |
| 10.2 | Ethernet stress | 1 | 1 | 1 |
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