| Item | Consideration from book "Computer Circuits Electrical Design" | Status |
|---|---|---|
| 12.3.1 | Chip Electrical Considerations | |
| 1 | Choice of Technology | |
| 1.1 | CMOS/BiCMOS/TTL/ECL | |
| 1.2 | Gate array (channeled or sea of gates)/standard cell/full customer/megacell/programmable logic device/chipsets | |
| 1.3 | Chip dc and ac specifications | |
| 1.4 | What SPICE models are provided by the vendor? What models need to be developed in-house? | |
| 1.5 | Is there easy migration from the present technology? | |
| 1.6 | Is the technology well supported by EDA? | |
| 1.7 | When is the chip available for engineering samples? full production? | |
| 1.8 | At production, what is the turnaround time from tape release to chip received? | |
| 2 | Physical | |
| 2.1 | What is the minimum transistor feature size (gate length for CMOS ASICs)? | |
| 2.2 | Size: basic cell, chip, wafer, contact via, interconnect width, and spacing | |
| 2.3 | Number of metal layers (signal, power, ground) | |
| 2.4 | What is the resistance and capacitance per unit length of metallization? | |
| 2.5 | What is the pad pitch? | |
| 3 | Performance Issue | |
| 3.1 | What is the basic gate delay (unloaded/lightly loaded/fully loaded)? | |
| 3.2 | Does the chip toggle at the frequency targeted? | |
| 3.3 | Does chip meet timing requirements on critical paths? | |
| 3.4 | What are latch setup and hold times? | |
| 3.5 | What is the mean time between failure due to metastability? | |
| 3.6 | What is the delay process variation? | |
| 4 | Functionality Issues | |
| 4.1 | Is the gate library complete? | |
| 4.2 | Does the usable gate count meet the integration requirement? | |
| 4.3 | Does the chip pin count meet the I/O requirement? | |
| 4.4 | Does the clock distribution scheme meet the skew control reuqirement? | |
| 4.5 | Are special drivers deeded (for example, differential driver, long-distance driver, pull-up driver, bidirectional driver, chip reentry driver)? | |
| 4.6 | Are special macros needed (for example, scan- or test-related macros, translation macros between two different technologies, ring oscillators)? | |
| 4.7 | Is embedded RAM required? What size and word organization? | |
| 4.8 | How many outputs can switch simultaneously? | |
| 4.9 | What is the α particle noise immunity? |
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